The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for software controlled cache line replacement within a cache segment.
Cache memories are well known storage devices that help reduce the costs, in both time and energy, to access data from a main memory. The cache memory is a smaller, faster memory which stores copies of the data from frequently used main memory locations. Most processors have different independent caches, including an instruction cache and data cache, where the data cache is usually organized as a hierarchy of a plurality of cache levels, e.g., level 1 (L1) and level 2 (L2) caches. In processor architectures that utilize virtualized address spaces, a third type of cache memory, referred to as a translation lookaside buffer (TLB), may also be used to speed up virtual-to-physical address translation for both executable instructions and data. The TLB may be part of a memory management unit (MMU) associated with the processor and may operate in conjunction with a page table data structure that is used to store the mapping between virtual addresses and physical addresses, where virtual addresses are used by the accessing process and physical addresses are used by the hardware.
When a processor needs to read from or write to a location in main memory, the processor first performs a cache check operation to check whether a copy of that data is in the cache memory. If so, the processor immediately reads from or writes to the cache memory which tends to be much faster than reading from or writing to main memory.
Data is transferred between main memory and cache in blocks of fixed size called cache lines or cache blocks. When a cache line is copied from main memory into the cache, a cache entry is created that includes the copied data as well as the requested memory location, which is often times referred to as a tag. When the cache memory is checked, the cache is first checked for a corresponding entry, determined based on the tag, and then looks for the contents of the requested memory location in any cache lines that may contain that address. If the processor finds the memory location is in the cache, a cache hit has occurred and the data may be accessed from the cache line. If the processor does not find the memory location in the cache, then a cache miss has occurred and a new cache entry is created and data from the main memory corresponding to the memory location is copied into the cache.
Cache memories are generally provided in two varieties, i.e. direct mapped cache and associative cache, which are based on the replacement policy implemented by the cache memory. With direct mapped caches, data from a main memory can be placed in only one place in the cache, i.e. each location in main memory can be cached by just one cache entry. With associative caches, the replacement policy implement is free to choose any entry in the cache to hold the copy of the data. In some caches, a compromise between direct mapped and associative caches is implemented in which each location in the main memory can go to any one of N places in the cache. These compromise cache structures are referred to as N-way set associative caches.